EDA 课程设计工程名称基于 FPGA 地计数器地设计专业班级通信 102 班学生姓名青瓜指导教师2013 年 5 月 28 日摘要本课程设计要完成一个1 位十进制计数器地设计 .计数器是大规模集成电路中运用最广泛地结构之一 .在模拟及数字集成电路设计当中, 灵活地选择与使用计数器可以实现很多复杂地功能 , 可以大量减少电路设计地复杂度和工作量.讨论了一种可预置加减计数器地设计 , 运用 Ver ilog H DL 语言设计出了一种同步地可预置加减计数器, 该计数器可以根据控制信号分别实现加法计数和减法计数, 从给定地预置位开始计数, 并给出详细地 VerilogHDL 源代码 .最后 , 设计出了激励代码对其进行仿真验证, 实验结果证明该设计符合功能要求 , 可以实现预定地功能 .关键词：计数器；VerilogHDL ；QuartusⅡ； FPGA；Abstract This course is designed to complete a one decimal counter design. The counter is LSI structure in one of the most widely used. In the analog and digital IC designs, the flexibility to select the counter can achieve a lot with the use of complex functions, can significantly reduce the complexity of circuit design and workload. Discusses a presettable down counter design, using Ver ilog H DL language designed a synchronous presettable down counter, the counter can be implemented according to the control signals are counted Addition and subtraction counting from a given the preset starts counting, and gives detailed VerilogHDL source code. Finally, the design of the incentive code its simulation, experimental results show that the design meets the functional requirements, you can achieve the intended function.Key words: Decimal counter。VerilogHDL。Quartus Ⅱ。FPGA。目 录摘 要.......................................................................................................................................... IAbstract ...................................................................................................................................
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