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电子琴毕业设计文献资料翻译VIP专享VIP免费

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第1页共12页编号:时间:2021年x月x日书山有路勤为径,学海无涯苦作舟页码:第1页共12页南京工程学院毕业设计文献资料翻译(原文及译文)原文名称:AT89C51Manual课题名称:基于单片机的电子琴设计学生姓名:高俊学号:240063216指导老师:宋宇飞所在系部:康尼学院专业名称:电子信息工程2010年3月20日第2页共12页第1页共12页编号:时间:2021年x月x日书山有路勤为径,学海无涯苦作舟页码:第2页共12页IntroductiontoAT89C51GENERALDESCRIPTIONTheAT89C51isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashProgrammableandErasableReadOnlyMemory(PEROM).ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandardMCS-51™instruction-setandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C51isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.Features•CompatiblewithMCS-51™Products•4KBytesofIn-SystemReprogrammableFlashMemory–Endurance:1,000Write/EraseCycles•FullyStaticOperation:0Hzto24MHz•Three-LevelProgramMemoryLock•128x8-BitInternalRAM•32ProgrammableI/OLines•Two16-BitTimer/Counters•SixInterruptSources•ProgrammableSerialChannel•LowPowerIdleandPowerDownModesTheAT89C51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.第3页共12页第2页共12页编号:时间:2021年x月x日书山有路勤为径,学海无涯苦作舟页码:第3页共12页第4页共12页第3页共12页编号:时间:2021年x月x日书山有路勤为径,学海无涯苦作舟页码:第4页共12页VCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX...

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